The Influence of Silicon Area on the Performance of the Full Adders

Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as 10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder implementation and, as a result, the delay time and power dissipation are significantly decreased. In order, to show the influence of the silicon area and transistors count on the performance of the 10-T full adder, it is compared to the most recent full adders : 28-T , 20T , 16-T , and 14 –T. Simulation result based on HSPICE simulator using 16nm technology showed that the 10-T XNOR full adder significantly improved the performance of full adder through decreasing the transistors count. In addition using the multi-supply voltage of 130nm technology, in this case the proposed full adder demonstrated is the best power consumption in comparison to other designs.